A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. That is, as flash memory technology progresses, the speed and memory density becomes higher and higher. Modern flash memory units are characterized by the non-volatility of the charge stored in the arrays of memory cells that make up the memory unit.
Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). These core memory devices can comprise a floating gate device where a conductive charge storing region (or floating gate) is located between a conductive wordline and a channel region of a substrate. The channel region is laterally disposed between a pair of bitlines. The floating gate can be separated from the wordline and the channel region by respective dielectric layers. In an alternative arrangement, the floating gate can be replaced by a non-conductive charge storing layer that can store data in plural charge storing regions. For example, a normal bit can be stored using a charge storing region adjacent a first bitline associated with the memory device and a complimentary bit can be stored using a charge storing region adjacent a second bitline associated with the memory device.
Programming of the foregoing memory devices can be accomplished, for example, by hot electron injection. Hot electron injection involves “pulsing” the device by applying appropriate voltage potentials to each of the wordline (the wordline connected to or defining a control gate of the memory device) and a drain of the memory device for a specified duration. During the programming pulse, a bias potential can be applied to the source to assist in controlling the amount of charge injected into the memory device.
In addition to increasing the data storage density of flash memory units, there has been a trend toward low power applications. For instance, some applications provide operating voltage (Vcc) as small as 1.8 volts. In these applications, control logic associated with the core memory array may not behave as desired. For instance, in low power applications, a pass transistor that couples the source bias potential (e.g., about 0.8 volts) to the source of the memory device(s) being programmed may be driven with a voltage that does not fully turn on the pass transistor. As a result, the potential at the source junction of the memory device(s) being programmed can rise, thereby lowering a voltage difference between the drain and the source of the memory device being programmed. This condition leads to slower programming of the memory device and potential failure of automatic program disturb (APD). APD, which is also referred to as automatic program disturb after erase (APDE), is a process that corrects for such over-erased flash memory cells. During an APD process, sufficient charge carriers (e.g., electrons) are reinjected into the charge storing layer after an erase process to restore the threshold voltage of the over-erased flash memory cells.
Accordingly, there is a demand for a flash memory unit and method of programming that is capable of applying a desired source side bias during programming in low power applications.